; ; H8/2148 ; ; Updated April, 2004 ; 1. Several and various corrections, including those following. ; 2. Corrected opcode generation for "mov.b @(#32, ers), erd" ; 3. Corrected opcode generation for "mov.b ers, @(#32, erd)" ; ; Updated 4th January, 2003 ; 1. Corrected op-code for long version of BRA instruction. ; 2. Commented-out one of the addressing modes for branch ; instructions in order to force all branches to use ; the long addressing mode unless short addressing is ; specifically requested with the :8 suffix or the ## ; prefix. ; ; Updated 25th December, 2002: ; 1. All the long branch instructions were being generated ; incorrectly using the short branch op codes and a ; sixteen bit offset. Created a new section of op-codes ; to force long branch instructions to generate the ; correct op-codes. ; ; Updated 14th November, 2002: ; 1. Corrected range of @aa:16 addressing for normal and ; advanced operating modes. ; 2. Corrected use of MOV Rn.W, @Rn instruction ; 3. Corrected use of DEC #2,Rn and INC #2,Rn instructions. ; ; Updated 13th November 2002: ; 1. Consolidated indirect and absolute addressing modes for ; all MOV instructions (8, 16 & 32 bit). ; 2. Added TRAPA #x instructions. ; 3. Added TAS @ERd instructions. ; ; Updated 12th November 2002: ; 1. Renumbered register definitions, operand definitions ; and various addressing mode definitions. ; 2. Added long branches and consolidated branch mnemonics. ; 3. Added 8-bit instructions for EXR flag register. ; 4. Consolidated all shift and rotate instructions and ; added all variants (8,16 & 32 bit operands). ; 5. Completed all addressing modes for bit manipulation ; instructions (eg BNOT, BCLR, BIXOR, ...). ; 6. Added CLRMAC instruction for H8/26XX CPU. ; 7. Consolidated addressing modes for JMP and JSR instructions ; and made provision for 24 bit addressing. ; ; Updated 22nd March: ; 1. added more 32-bit instructions. ; Created on 18th March 2002 ; This is a work-in-progress. It is NOT complete and even ; what has been done might not be correct. ; When changing modes, search for "*mode*" to find all the ; lines that ought to be modified. ; --------------------------------------------------------------- ]; REGISTERS ; (Normal *mode*) ;9001, "R0","R1","R2","R3","R4","R5","R6","SP" ;9002, "R0","R1","R2","R3","R4","R5","R6","SP", "E0","E1","E2","E3","E4","E5","E6","E7" ;9006, "R0H","R1H","R2H","R3H","R4H","R5H","R6H","R7H", "R0L","R1L","R2L","R3L","R4L","R5L","R6L","R7L" ;9008, "ER0","ER1","ER2","ER3","ER4","ER5","ER6","ER7", "ER0","ER1","ER2","ER3","ER4","ER5","ER6","ESP" ; (Expanded *mode*) 9001, "R0","R1","R2","R3","R4","R5","R6","R7" 9002, "R0","R1","R2","R3","R4","R5","R6","R7", "E0","E1","E2","E3","E4","E5","E6","E7" 9006, "R0H","R1H","R2H","R3H","R4H","R5H","R6H","R7H", "R0L","R1L","R2L","R3L","R4L","R5L","R6L","R7L" 9008, "ER0","ER1","ER2","ER3","ER4","ER5","ER6","ER7", "ER0","ER1","ER2","ER3","ER4","ER5","ER6","SP" ; The following lines define the set of registers for @ERd. This will ; alter depending on what operating mode the CPU is using. In the ; "normal" mode with a 16-bit address space the @ERd register set is ; the eight 16-bit registers from r0 to r7 inclusive. In the "advanced" ; mode the ERd register set is the eight registers from ER0 to ER7 ; inclusive. ;(normal *mode*) ;9100, "R0","R1","R2","R3","R4","R5","R6","R7", "R0","R1","R2","R3","R4","R5","R6","SP" ;(advanced *mode*) 9100, "ER0","ER1","ER2","ER3","ER4","ER5","ER6","ER7", "ER0","ER1","ER2","ER3","ER4","ER5","ER6","SP" ; --------------------------------------------------------------- * OPERANDS ;NUM START LENGTH EXP LOW HIGH COMMENT 6000, 9, 3, @9001, 0, 7 ; R0-SP (eight registers) 6020, 13, 3, @9001, 0, 7 6030, 8, 4, @9002, 0, 15 ; R0-E7 (sixteen registers) 6040, 12, 4, @9002, 0, 15 6048, 24, 4, @9002, 0, 15 6050, 28, 4, @9002, 0, 15 6060, 4, 4, @9006, 0, 15 ; R0H-SPL 6070, 8, 4, @9006, 0, 15 6080, 12, 4, @9006, 0, 15 6090, 24, 4, @9006, 0, 15 6091, 28, 4, @9006, 0, 15 6092, 40, 4, @9006, 0, 15 6094, 56, 4, @9006, 0, 15 6100, 8, 8, #, -32768, 65535 ; #@xx:8 ;6130, 8, 8, #-$FF00, $FF00, $FFFF ; @aa:8 (normal *mode*) 6130, 8, 8,#-$00FFFF00, $00FFFF00, $00FFFFFF; @aa:8 (advanced *mode*) ; The range of the @aa:16 addressing mode changes according ; to the CPU mode. ; Normal mode, the range is ; from $0000 to $FFFF ; Advanced mode, the range is split into two ranges, ; from $00000000 to $00007FFF ; from $FFFF8000 to $FFFFFFFF ;6160, 16, 16, #, 0, $7FFF ; @aa:16 16-bit address ; (normal *mode*) ;6162, 16, 16, #, $08000, $FFFF ; @aa:16 16-bit address ; (advanced *mode*) ;6162, 16, 16,#-$FFFF0000,$FFFF8000,$FFFFFFFF ; @aa:16 16-bit addressing 6170, 16, 16, #, -32768, 65535 ; #xx:16 displacement 6180, 32, 16, #, $0000, $7FFF ; @aa:16 used by 32-bit instructions ;6182, 32, 16,#-$00FF0000,$00FF8000,$00FFFFFF ; @aa:16 used by 32-bit instructions 6200, 8, 24, #, 0, $FFFFFF ; 24-bit address @aa:24 6270, 8, 8, #, -128, 255 ; #xx ;6275, 16, 8, #, -128, 255 ; #xx 6280, 24, 8, #, -128, 255 ; #xx ;NUM START LENGTH EXP LOW HIGH COMMENT 6310, 8, 8, #-$-`, $+`-128, $+`+126 ; d:8 6315, 8, 8, #, -10, +8 ; mws addition for branches 6320, 16, 16, #-$-`, $+`-32768, $+`+32766 ; d:16 6430, 9, 3, #, 0, 7 ; #xx:3 6440, 25, 3, #, 0, 7 ; 6450, 41, 3, #, 0, 7 ; 6460, 57, 3, #, 0, 7 ; 6500, 9, 3, @9100, 0, 15 ; @ERd ; 32-bit operands 6600, 13, 3, @9008, 0, 15 ; ER0-ER7 6610, 25, 3, @9008, 0, 15 ; ER0-ER7 6620, 29, 3, @9008, 0, 15 ; ER0-ER7 6630, 45, 3, @9008, 0, 15 ; ER0-ER7 6640, 9, 3, @9008, 0, 15 ; ER0-ER7 6650, 16, 32, #, -2147483648, 2147483647 ; #xx:32 6660, 32, 32, #, -2147483648, 2147483647 ; #aa:32 6670, 48, 32, #, -2147483648, 2147483647 ; #dd:32 ; --------------------------------------------------------------- * ADDRESSING MODES 1, {6270}:8,{6060}^0000: ;#xx:8,Rd 2, {6270},{6060}^0000: ; " 3, {6070},{6080}^0000: ;.B Rs,Rd 4, {6030},{6040}^0000: ;.W Rs,Rd 10, {6070},{6020}^0000: ; Rs, Rd 11, {6090},{6050}^00: ; Rs, Rd ;35, {6160},{6080}^6A000000: ; @aa:16,Rd ;36, {6162},{6080}^6A000000: ; " 45, {6170}:16,{6040}^00000000: ; #xx:16, Rd 46, {6170},{6040}^00000000: ; #xx:16, Rd 53, {6040},@({6170}:16,{6500})^6F800000: ; Rs,@(d:16,ERd) 54, {6040},@({6170},{6500})^6F800000: ; " 55, {6040},@-{6500}^6D80: ; Rs,@-ERd 56, {6040},@{6500}^6980: ; Rs,@ERd ;57, {6040},@{6160}^6B800000: ; Rs,@aa:16 ;58, {6040},@{6162}^6B800000: ; " ; Addressing modes for the CCR and EXR registers. 1010, #{6280},EXR^01410400: ; #xx:8, EXR 1020, #{6270},CCR^0400: ; #xx:8, CCR 1030, {6080},CCR^0000: ; Rs, CCR 1040, {6080},EXR^0010: ; Rs, EXR ; Addressing modes for the bit manipulation instructions. 1110, {6430},{6080}^0000: ; #xx:3, Rd 1120, {6440},@{6500}^00000000: ; #xx:3, @ERd 1130, {6440},@{6130}^02000000: ; #xx:3, @aa:8 ;1140, {6450},@{6160}^6A1000000000: ; #xx:3, @aa:16 ;1142, {6450},@{6162}^6A1000000000: ; #xx:3, @aa:16 1150, {6460},@{6650}^6A30000000000000:; #xx:3, @aa:32 2110, {6070},{6080}^0000: ; .B Rs,Rd 2120, {6090},@{6500}^00: ; Rn, @ERd 2130, {6090},@{6130}^02: ; Rn, @aa:8 ;2140, {6092},@{6160}^6A1000000000: ; Rn, @aa:16 ;2142, {6092},@{6160}^6A1000000000: ; Rn, @aa:16 2150, {6094},@{6650}^6A30000000000000:; Rn, @aa:32 ; Addressing modes for JMP & JSR 1310, @{6500}^01: ; Register indirect (jmp @ERn) 1320, @{6200}^02000000: ; Absolute address 1321, {6200}^02000000: ; Absolute address (mws preferred style, without leading @) 1330, @@{6270}^03: ; Page 0 indirect. ; Addressing modes for the branch instructions 1410, {6310}:8^0000: ; Branch with 8-bit displacement ;1420, {6310}^0000: ; Removing this forces all branches to be long unless explicitly made short. 1430, ##{6315}^0000: ; Bcc MWS modification, ## makes easy to find 1440, ##{6315}:8^0000: ; 1470, {6320}^00000000: ; Branch with 16-bit displacement 1480, {6320}:16^00000000: ; 1500, {6080}^0000: ; .B Rd 1501, #1,{6080}^0000: ; .B Rd 1502, #2,{6080}^0040: ; .B Rd ; Addressing modes for MOV:8 1610, @({6170},{6500}),{6080}^6E000000: ; @(d:16, ERs), Rd.B 1612, @({6660},{6500}),{6091}^78006A2000000000: ; @(d:32, ERs), Rd.B 1614, @{6500},{6080}^68: ; @ERs, Rd.B 1616, @{6500}+,{6080}^6C: ; @ERs+, Rd.B 1618, @{6130},{6060}^2000: ; @aa:8, Rd.B ;1620, @{6160},{6080}^6A000000: ; @aa:16, Rd.B ;1622, @{6162},{6080}^6A000000: ; @aa:16, Rd.B 1624, @{6650},{6080}^6A2000000000: ; @aa:32, Rd.B 1710, {6080},@({6170},{6500})^6E800000: ; Rs.B, @(d:16, ERd) 1712, {6091},@({6660},{6500})^78006AA000000000: ; Rs.B, @(d:32, ERd) 1714, {6080},@{6500}^6880: ; Rs.B, @ERd 1716, {6080},@-{6500}^6C80: ; Rs.B, @-ERd 1718, {6060},@{6130}^3000: ; Rs.B, @aa:8 ;1720, {6080},@{6160}^6A800000: ; Rs.B, @aa:16 ;1722, {6080},@{6162}^6A800000: ; Rs.B, @aa:16 1724, {6080},@{6650}^6AA000000000: ; Rs.B, @aa:32 2500, {6040}^0000: ; .W Rd 2501, #1,{6040}^0000: ; .W Rd 2502, #2,{6040}^0040: ; .W Rd ; Addressing modes for MOV:16 2610, @({6170},{6500}),{6040}^6F000000: ; @(d:16, ERs), Rd.W 2612, @({6660},{6500}),{6050}^78006B2000000000: ; @(d:32, ERs), Rd.W 2614, @{6500},{6040}^6900: ; @ERs, Rd.W 2616, @{6500}+,{6040}^6D00: ; @ERs+, Rd.W ;2620, @{6160},{6040}^6B000000: ; @aa:16, Rd.W ;2622, @{6162},{6040}^6B000000: ; @aa:16, Rd.W 2624, @{6650},{6040}^6B2000000000: ; @aa:32, Rd.W 2710, {6040},@({6170},{6500})^6F800000: ; Rd.W, @(d:16, ERs) 2712, {6050},@({6660},{6500})^78006BA000000000: ; Rd.W, @(d:32, ERs) 2714, {6040},@{6500}^6980: ; Rd.W, @ERs 2716, {6040},@-{6500}^6D80: ; Rd.W, @ERs+ ;2720, {6040},@{6160}^6B800000: ; Rd.W, @aa:16 ;2722, {6040},@{6162}^6B800000: ; Rd.W, @aa:16 2724, {6040},@{6650}^6BA000000000: ; Rd.W, @aa:32 ; Addressing modes for MOV:32 3610, @({6180},{6610}),{6620}^01006F000000: ; @(d:16, ERs), Rd.L 3612, @({6670},{6610}),{6630}^010078006B2000000000:; @(d:32, ERs), Rd.L 3614, @{6610},{6620}^01006900: ; @ERs, Rd.L 3616, @{6610}+,{6620}^01006D00: ; @ERs+, Rd.L ;3620, @{6180},{6620}^01006B000000: ; @aa:16, Rd.L ;3622, @{6182},{6620}^01006B000000: ; @aa:16, Rd.L 3624, @{6660},{6620}^01006B2000000000: ; @aa:32, Rd.L 3710, {6620},@({6180},{6610})^01006F800000: ; Rd.L, @(d:16, ERs) 3712, {6630},@({6670},{6610})^010078006BA000000000:; Rd.L, @(d:32, ERs) 3714, {6620},@{6610}^01006980: ; Rd.L, @ERs 3716, {6620},@-{6610}^01006D80: ; Rd.L, @-ERs ;3720, {6620},@{6180}^01006B800000: ; Rd.L, @aa:16 ;3722, {6620},@{6182}^01006B800000: ; Rd.L, @aa:16 3724, {6620},@{6660}^01006BA000000000: ; Rd.L, @aa:32 ;3150, {6620},@({6180},{6610})^00000000: ; ERs, @(d:16, ERd) ;3152, {6630},@({6670},{6610})^000000000000: ; ERs, @(d:32, ERd) ;3160, {6620},@-{6610}^00000000: ; ERs,@-ERd ;3170, {6620},@{6610}^00000000: ; ERs, @ERs ; 32-bit addressing modes 3100, {6650},{6600}^000000000000: ; 32-bit immediate 3104, {6620}^00000000: ; eg PUSH.L and POP.L 3107, {6640},{6600}^0000: ; Register direct 3108, {6610},{6620}^00000000: ; Register direct 3200, {6030},{6600}^0000: ; Rs, ERd (eg MULXU.W) 3210, {6048},{6620}^00: ; Rs, ERd (eg MULXS.W) 3500, {6600}^0000: ; Register direct 3501, #1,{6600}^0000: 3502, #2,{6600}^0040: ; There are more 32-bit addressing modes to be defined ; --------------------------------------------------------------- * MNEMONICS ; MULXS.B Need to create register definitions ; MULXS.W Ditto ADD #|1-2^80: ADD #|3100^7A10: ; 32-bit immediate ADD #|45-46^79100000: ADD |3107^0A80: ; 32-bit register direct ADD |3^08: ADD |4^09: ADD.B #|1-2^8000: ADD.B |3^0800: ADD.W #|45-46^79100000: ADD.W |4^0900: ADDS #1,|3500^0B00: ; 32-bit register direct ADDS #2,|3500^0B80: ; 32-bit register direct ADDS #4,|3500^0B90: ; 32-bit register direct ADDX #|1-2^90: ADDX |3^0E: AND #|1-2^E0: ; 8-bit immediate AND #|3100^7A60: ; 32-bit immediate AND #|45-46^79600000: ; 16-bit immediate AND |3108^01F06600: ; 32-bit register direct AND |3^16: ; 8-bit register direct AND |4^66: ; 16-bit register direct ANDC |1010^000006: ANDC |1020^06: BCC |1410-1440^44: BCS |1410-1440^45: BEQ |1410-1440^47: BF |1410-1440^41: BGE |1410-1440^4C: BGT |1410-1440^4E: BHI |1410-1440^42: BHS |1410-1440^44: BLE |1410-1440^4F: BLO |1410-1440^45: BLS |1410-1440^43: BLT |1410-1440^4D: BMI |1410-1440^4B: BNE |1410-1440^46: BNZ |1410-1440^46: BPL |1410-1440^4A: BRA |1410-1440^40: BRN |1410-1440^41: BSR |1410-1440^55: BT |1410-1440^40: BVC |1410-1440^48: BVS |1410-1440^49: BZ |1410-1440^47: BCC |1470-1480^5840: BCS |1470-1480^5850: BEQ |1470-1480^5870: BF |1470-1480^5810: BGE |1470-1480^58C0: BGT |1470-1480^58E0: BHI |1470-1480^5820: BHS |1470-1480^5840: BLE |1470-1480^58F0: BLO |1470-1480^5850: BLS |1470-1480^5830: BLT |1470-1480^58D0: BMI |1470-1480^58B0: BNE |1470-1480^5860: BNZ |1470-1480^5860: BPL |1470-1480^58A0: BRA |1470-1480^5800: BRN |1470-1480^5810: BSR |1470-1480^5C00: BT |1470-1480^5800: BVC |1470-1480^5880: BVS |1470-1480^5890: BZ |1470-1480^5870: BAND #|1110^7600: BAND #|1120-1130^7C007600: BAND #|1140^000000007600: BAND #|1150^0000000000007600: BCLR #|1110^7200: BCLR #|1120-1130^7D007200: BCLR #|1140^000800007200: BCLR #|1150^0008000000007200: BCLR |2110^6200: BCLR |2120-2130^7D006200: BCLR |2140^000800006200: BCLR |2150^0008000000006200: BIAND #|1110^7680: BIAND #|1120-1130^7C007680: BIAND #|1140^000000007680: BIAND #|1150^0000000000007680: BILD #|1110^7780: BILD #|1120-1130^7C007780: BILD #|1140^000000007780: BILD #|1150^0000000000007780: BIOR #|1110^7480: BIOR #|1120-1130^7C007480: BIOR #|1140^000000007480: BIOR #|1150^0000000000007480: BIST #|1110^6780: BIST #|1120-1130^7D006780: BIST #|1140^000800006780: BIST #|1150^0008000000006780: BIXOR #|1110^7580: BIXOR #|1120-1130^7C007580: BIXOR #|1140^000000007580: BIXOR #|1150^0000000000007580: BLD #|1110^7700: BLD #|1120-1130^7C007700: BLD #|1140^000000007700: BLD #|1150^0000000000007700: BNOT #|1110^7100: BNOT #|1120-1130^7D007100: BNOT #|1140^000800007100: BNOT #|1150^0008000000007100: BNOT |2110^6100: BNOT |2120-2130^7D006100: BNOT |2140^000800006100: BNOT |2150^0008000000006100: BOR #|1110^7400: BOR #|1120-1130^7C007400: BOR #|1140^000000007400: BOR #|1150^0000000000007400: BSET #|1110^7000: BSET #|1120-1130^7D007000: BSET #|1140^000800007000: BSET #|1150^0008000000007000: BSET |2110^6000: BSET |2120-2130^7D006000: BSET |2140^000800006000: BSET |2150^0008000000006000: BST #|1110^6700: BST #|1120-1130^7D006700: BST #|1140^000800006700: BST #|1150^0008000000006700: BTST #|1110^7300: BTST #|1120-1130^7C007300: BTST #|1140^000000007300: BTST #|1150^0000000000007300: BTST |2110^6300: BTST |2120-2130^7C006300: BTST |2140^000000006300: BTST |2150^0000000000006300: BXOR #|1110^7500: BXOR #|1120-1130^7C007500: BXOR #|1140^000000007500: BXOR #|1150^0000000000007500: CLRMAC ^01A0: CMP #|1-2^A0: CMP #|3100^7A20: ; 32-bit immediate CMP #|45-46^79200000: CMP |3107^1F80: ; 32-bit register direct CMP |3^1C: CMP |4^1D: DAA |1500^0F: DAS |1500^1F: DEC |1500^1A: ; 8-bit DEC |2500-2501^1B50: ; 16-bit DEC #2,|2500^1BD0: ; 16-bit DEC |3500-3501^1B70: ; 32-bit DEC #2,|3500^1BF0: ; 32-bit DIVXS |11^01D05100: DIVXS |3210^01D05300: DIVXU |10^51: DIVXU |3200^5300: EEPMOV ^7B5C598F: EXTS |3500^17F0: ; 32-bit register direct EXTS |2500^17D0: ; 16-bit register direct EXTU |3500^1770: ; 32-bit register direct EXTU |2500^1750: ; 16-bit register direct INC |1500^0A: ; 8-bit INC |2500-2501^0B50: ; 16-bit INC #2,|2500^0BD0: ; 16-bit INC |3500-3501^0B70: ; 32-bit INC #2,|3500^0BF0: ; 32-bit JMP |1310-1330^5800: JSR |1310-1330^5C00: LDC |1010^000003: LDC |1020-1040^03: MOV #|1-2^F000: ; 8-bit transfer -> Rd.B MOV #|45-46^79000000: ; 16-bit transfers -> Rd.W MOV #|3100^7A00: ; 32-bit transfer -> Rd.L MOV |1610-1724^0000: ; 8-bit indirect transfers MOV |2610-2724^0000: ; 16-bit indirect transfers MOV |3610-3724^0000: ; 32-bit indirect transfers ;MOV |3150^01006F800000: ; ERs, @(d:16, ERd) 32b reg indirect, 16b offset ;MOV |3152^010078006BA0: ; ERs, @(d:32, ERd) 32b reg indirect, 32b offset ;MOV |3160^01006D80: ; ERs, @-ERd 32b register indirect pre-decrement ;MOV |3170^01006980: ; ERs, @ERd 32b register indirect MOV |3^0C: ; .B Rs, Rd MOV |4^0D: ; .W Rs, Rd MOV |3107^0F80: ; .L ERs, ERd ;MOV |53-58^00: ; .W -> Rd.W MOVFPE @|35-36^6A40: MOVTPE |43-44^6AC0: MULXS |11^01D05000: MULXS |3210^01D05200: MULXU |10^50: MULXU |3200^5200: NEG |3500^17B0: ; 32-bit NEG |1500^1780: ; 8-bit NEG |2500^1790: ; 16-bit NOP ^0000: NOT |3500^1730: ; 32-bit NOT |1500^1700: ; 8-bit NOT |2500^1710: ; 16-bit OR #|1-2^C0: OR #|3100^7A40: ; 32-bit immediate OR #|45-46^79400000: ; 16-bit immediate OR |3108^01F06400: ; 32-bit register direct OR |3^14: OR |4^64: ; 16-bit register to register ORC |1010-1020^00: POP |3104^01006D70: ; Registers ER0 to ER7 POP |2500^6D70: ; Registers R0 to E7 PUSH |3104^01006DF0: ; Registers ER0 to ER7 PUSH |2500^6DF0: ; Registers R0 to E7 ROTL |1500-1502^1280: ; 8-bit ROTL |2500-2502^1290: ; 16-bit ROTL |3500-3502^12B0: ; 32-bit ROTR |1500-1502^1380: ; 8-bit ROTR |2500-2502^1390: ; 16-bit ROTR |3500-3502^13B0: ; 32-bit ROTXL |1500-1502^1200: ; 8-bit ROTXL |2500-2502^1210: ; 16-bit ROTXL |2500-2502^1230: ; 32-bit ROTXR |1500-1502^1300: ; 8-bit ROTXR |2500-2502^1310: ; 16-bit ROTXR |3500-3502^1330: ; 32-bit RTE ^5670: RTS ^5470: SHAL |1500-1502^1080: ; 8-bit SHAL |2500-2502^1090: ; 16-bit SHAL |3500-3502^10B0: ; 32-bit SHAR |1500-1502^1180: ; 8-bit SHAR |2500-2502^1190: ; 16-bit SHAR |3500-3502^11B0: ; 32-bit SHLL |1500-1502^1000: ; 8-bit SHLL |2500-2502^1010: ; 16-bit SHLL |3500-3502^1030: ; 32-bit SHLR |1500-1502^1100: ; 8-bit SHLR |2500-2502^1110: ; 16-bit SHLR |3500-3502^1130: ; 32-bit SLEEP ^0180: STC CCR,|1500^0200: STC EXR,|1500^0210: SUB #|3100^7A30: ; 32-bit immediate SUB #|45-46^79300000: SUB |3107^1A80: ; 32-bit register direct SUB |3^18: SUB |4^19: SUB.B |3^18: SUB.W #|45-46^79300000: SUB.W |4^19: SUBS #1,|3500^1B00: ; 32-bit register direct SUBS #2,|3500^1B80: ; 32-bit register direct SUBS #4,|3500^1B90: ; 32-bit register direct SUBX #|1-2^B0: SUBX |3^1E: TAS @ER0^01E07B0C: TAS @ER1^01E07B1C: TAS @ER4^01E07B4C: TAS @ER5^01E07B5C: TRAPA #0^5700: TRAPA #1^5710: TRAPA #2^5720: TRAPA #3^5730: XOR #|1-2^D0: XOR #|3100^7A50: ; 32-bit immediate XOR #|45-46^79500000: XOR |3108^01F06500: ; 32-bit register direct XOR |3^15: XOR |4^65: XORC |1010-1011^05: